How To Write A 12 Bit Register In Verilog

		Introduction
		Every new learner'south dream is to understand Verilog in 1 day, at least enough to use it. The next few pages are my attempt to make this dream a reality. In that location will be some theory and examples followed by some exercises. This tutorial will non teach you how to program; it is designed for those with some programming experience. Even though Verilog executes different code blocks concurrently as opposed to the sequential execution of most programming languages, there are even so many parallels. Some background in digital design is likewise helpful.
		Life before Verilog was a life full of schematics. Every design, regardless of complexity, was designed through schematics. They were difficult to verify and mistake-decumbent, resulting in long, wearisome evolution cycles of blueprint, verification... blueprint, verification... blueprint, verification...
		When Verilog arrived, we all of a sudden had a unlike mode of thinking about logic circuits. The Verilog blueprint cycle is more similar a traditional programming i, and information technology is what this tutorial volition walk you lot through. Here's how it goes:
		Specifications (specs) Loftier level design Depression level (micro) design RTL coding Verification Synthesis.
		First on the list is specifications - what are the restrictions and requirements we will place on our pattern? What are we trying to build? For this tutorial, we'll exist building a two agent czar: a device that selects among two agents competing for mastership. Hither are some specs nosotros might write upwards.
		Two agent arbiter. Active high asynchronous reset. Fixed priority, with agent 0 having priority over agent 1 Grant will exist asserted as long as request is asserted.
		Once nosotros have the specs, we can draw the block diagram, which is basically an abstraction of the data catamenia through a system (what goes into or comes out of the black boxes?). Since the example that nosotros take taken is a uncomplicated 1, we can have a block diagram as shown below. We don't worry about what'due south inside the magical black boxes simply yet.
		Block diagram of arbiter
		Now, if we were designing this machine without Verilog, the standard procedure would dictate that nosotros depict a state machine. From there, we'd brand a truth tabular array with land transitions for each flip-flop. And after that we'd depict Karnaugh maps, and from K-maps we could get the optimized circuit. This method works just fine for small designs, but with big designs this flow becomes complicated and error prone. This is where Verilog comes in and shows the states another manner.
		Low level design
		To see how Verilog helps us pattern our arbiter, let'due south become on to our state motorcar - now we're getting into the depression-level blueprint and peeling abroad the embrace of the previous diagram'due south blackness box to see how our inputs bear on the machine.
		Each of the circles represents a state that the machine can be in. Each state corresponds to an output. The arrows between the states are land transitions, labeled by the result that causes the transition. For instance, the leftmost orange arrow ways that if the machine is in state GNT0 (outputting the signal that corresponds to GNT0) and receives an input of !req_0, the machine moves to state IDLE and outputs the signal that corresponds to that. This state machine describes all the logic of the organisation that yous'll need. The adjacent step is to put it all in Verilog.
		Modules
		Nosotros'll need to backtrack a flake to practice this. If you expect at the arbiter cake in the first picture, we can see that it has got a name ("czar") and input/output ports (req_0, req_1, gnt_0, and gnt_1).
		Since Verilog is a HDL (hardware clarification language - one used for the conceptual pattern of integrated circuits), it also needs to have these things. In Verilog, we phone call our "black boxes" module. This is a reserved word within the programme used to refer to things with inputs, outputs, and internal logic workings; they're the rough equivalents of functions with returns in other programming languages.
		Lawmaking of module "czar"
		If you wait closely at the arbiter block we encounter that there are pointer marks, (incoming for inputs and approachable for outputs). In Verilog, after nosotros have alleged the module name and port names, nosotros tin ascertain the direction of each port. (version note: In Verilog 2001 we tin can ascertain ports and port directions at the same fourth dimension) The code for this is shown below.
		i module arbiter ( 2 // Two slashes make a comment line. iii clock , // clock iv reset , // Active high, syn reset 5 req_0 , // Request 0 6 req_1 , // Asking 1 seven gnt_0 , // Grant 0 8 gnt_1 // Grant 1 9 ); 10 //-------------Input Ports----------------------------- 11 // Note : all commands are semicolon-delimited 12 input clock ; 13 input reset ; 14 input req_0 ; 15 input req_1 ; 16 //-------------Output Ports---------------------------- 17 output gnt_0 ; eighteen output gnt_1 ; You lot could download file one_day1.v here
		Hither we have only two types of ports, input and output. In real life, we tin accept bi-directional ports as well. Verilog allows usa to ascertain bi-directional ports equally "inout."
		Bi-Directional Ports Example -
		inout read_enable; // port named read_enable is bi-directional
		How do you define vector signals (signals composed of sequences of more than ane scrap)? Verilog provides a simple way to ascertain these besides.
		Vector Signals Example -
		inout [7:0] address; //port "address" is bidirectional
		Note the [7:0] means we're using the piffling-endian convention - you start with 0 at the rightmost scrap to begin the vector, then motility to the left. If we had done [0:7], we would be using the big-endian convention and moving from left to right. Endianness is a purely capricious way of deciding which way your data will "read," but does differ between systems, and so using the right endianness consistently is important. Equally an analogy, think of some languages (English) that are written left-to-right (big-endian) versus others (Arabic) written correct-to-left (little-endian). Knowing which manner the language flows is crucial to being able to read it, but the management of menstruation itself was arbitrarily set years back.
		Summary
		Nosotros learnt how a block/module is divers in Verilog. Nosotros learnt how to define ports and port directions. We learnt how to declare vector/scalar ports.
		Information Blazon
		What do data types have to do with hardware? Aught, actually. People simply wanted to write one more language that had information types in it. It's completely gratuitous; there'southward no signal.
		But wait... hardware does accept two kinds of drivers.
		(Drivers? What are those?)
		A driver is a data type which tin bulldoze a load. Basically, in a concrete circuit, a driver would exist anything that electrons tin can move through/into.
		Driver that can store a value (example: flip-flop). Commuter that tin can not shop value, only connects two points (example: wire).
		The first type of commuter is called a reg in Verilog (brusque for "register"). The 2nd data type is called a wire (for... well, "wire"). Yous can refer to tidbits department to empathise it amend.
		In that location are lots of other data types - for instance, registers can be signed, unsigned, floating signal... as a newbie, don't worry about them right now.
		Examples :
		wire and_gate_output; // "and_gate_output" is a wire that merely outputs
		reg d_flip_flop_output; // "d_flip_flop_output" is a register; it stores and outputs a value
		reg [seven:0] address_bus; // "address_bus" is a niggling-endian 8-bit register
		Summary
		Wire data blazon is used for connecting two points. Reg data type is used for storing values. May god bless the balance of data types. You'll see them anytime.
		Operators
		Operators, thankfully, are the same things here as they are in other programming languages. They take two values and compare (or otherwise operate on) them to yield a tertiary result - mutual examples are add-on, equals, logical-and... To brand life easier for us, well-nigh all operators (at to the lowest degree the ones in the list beneath) are exactly the same as their counterparts in the C programming language.
		Operator Type Operator Symbol Operation Performed Arithmetic * Multiply / Division + Add - Subtract % Modulus + Unary plus - Unary minus Logical ! Logical negation && Logical and || Logical or Relational > Greater than < Less than >= Greater than or equal <= Less than or equal Equality == Equality != inequality Reduction ~ Bitwise negation ~& nand | or ~| nor ^ xor ^~ xnor ~^ xnor Shift >> Right shift << Left shift Concatenation { } Concatenation Conditional ? conditional
		Example -
		a = b + c ; // That was very easy a = 1 << 5; // Hum let me think, ok shift 'i' left by 5 positions. a = !b ; // Well does it capsize b??? a = ~b ; // How many times exercise you want to assign to 'a', it could cause multiple-drivers.
		Summary
		Let's attend the C language grooming once again, they're (almost) just similar the C ones.

How To Write A 12 Bit Register In Verilog,

Source: http://www.asic-world.com/verilog/verilog_one_day1.html

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